(China (Mainland))
Product Summary
The EP2S60F672C3 is one member of the Stratix II FPGA family which is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance. And the EP2S60F672C3 offers up to 9 Mbits of on-chip, TriMatrix memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384 (18-bit x 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions.
Parametrics
EP2S60F672C3 absolute maximum ratings:(1)Supply voltage: -0.5 to 1.8 V;(2)Analog power supply for PLLs: -0.5 to 1.8 V;(3)Digital power supply for PLLs: -0.5 to 1.8 V;(4)DC input voltage: -0.5 to 4.6 V;(5)DC output current, per pin: -25 to 40 mA;(6)Storage temperature: -65 to 150 °C;(7)Junction temperature: -55 to 125 °C.
Features
EP2S60F672C3 features:(1)15,600 to 179,400 equivalent LEs; (2)Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources; (3)TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers; (4)Up to 16 global clocks with 24 clocking resources per device region; (5)Support for design security using configuration bitstream encryption; (6)Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM Support for remote configuration updates; (7)Support for numerous single-ended and differential I/O standards; (8)High-speed differential I/O support with DPA circuitry for 1-Gbps performance.
Diagrams
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 EP2S60F672C3 |
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IC STRATIX II FPGA 60K 672-FBGA |
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EP2S60F672C3N |
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IC STRATIX II FPGA 60K 672-FBGA |
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